MPC860DEZQ50D4

Product Summary

The MPC860DEZQ50D4 is a Power Quad Integrated Communications Controller. It is a versatile one-chip integrated microprocessor and peripheral combination designed for a variety of controller applications. It particularly excels in communications and networking systems. The MPC860DEZQ50D4 is referred to as the MPC860 in this hardware specification. The MPC860DEZQ50D4 implements the PowerPC architecture and contains a superset of Freescale’s MC68360 Quad Integrated Communications Controller (QUICC), referred to here as the QUICC, RISC Communications Proccessor Module (CPM).

Parametrics

MPC860DEZQ50D4 absolute maximum ratings: (1)Supply voltage:VDDH:–0.3 to 4.0 V, VDDL:–0.3 to 4.0 V, KAPWR:–0.3 to 4.0 V, VDDSYN:–0.3 to 4.0 V; (2)Input voltage:GND–0.3V to VDDH; (3)Temperature (standard):TA(min):0℃, Tj(max):95℃; (4)Temperature (extended):TA(min):–40℃, Tj(max):95℃; (5)Storage temperature range:–55℃ to 150℃.

Features

MPC860DEZQ50D4 features: (1)The core performs branch prediction with conditional prefetch without conditional execution; (2)4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache; (3)MMUs with 32-entry TLB, fully-associative instruction, and data TLBs; (4)MMUs support multiple page sizes of 4-, 16-, and 512-Kbytes, and 8-Mbytes; 16 virtual address spaces and 16 protection groups; (5)Advanced on-chip-emulation debug mode; (6)Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits); (7)32 address lines; (8)Operates at up to 80 MHz; (9)Memory controller (eight banks): Contains complete dynamic RAM(DRAM) controller; (10)Each bank can be a chip select or RAS to support a DRAM bank; (11)Up to 15 wait states programmable per memory bank; (12)Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory devices; (13)DRAM controller programmable to support most size and speed memory interfaces; (14)Four CAS lines, four WE lines, and one OE line; (15)Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory); (16)Variable block sizes (32 Kbyte to 256 Mbyte); (17)Selectable write protection; (18)On-chip bus arbitration logic.

Diagrams